Thesis Committee Members:
Eric Fossum, Ph.D. (Chair)
Kofi Odami, Ph.D.
Jason Stauth, Ph.D.
Robert Henderson, Ph.D.

Abstract

The concept of quanta image sensors (QIS), high resolution image sensors with photon counting ability, was proposed to take advantage of shrinking pixel sizes due to semiconductor technology advancements. The key aspects of the single-bit QIS involve counting individual photoelectrons using tiny, spatially oversampled binary photodetectors at high readout rates, representing this binary output as a bit cube (x,y,t), and finally, processing the bit cubes to form high dynamic range images. A QIS may contain over a billion jots, each producing just 1mV/e- of signal, with a field readout rate 10-100 times faster than the conventional CMOS image sensors. Use of conventional CMOS imager readout circuits would result in high-power dissipation and impact sensor performance. The principal challenge addressed in this dissertation is the design of internal high-speed and low-power addressing and readout circuits for QISs.
Low-power design techniques are described for analog and digital circuits, and high-speed I/O pads. Charge-transfer amplifiers (CTA) are determined as a solution to reduce power consumption in analog circuits while providing enough speed (band-width). The introduced low-power design methods and techniques were implemented on four test chips. A modified CTA structure is proposed that reduces the power consumption of a conventional CTA by at least a factor of two. The implemented readout circuits in a 0.18μm CIS process as a megapixel and 1000fps binary imager resulted in 2.5pJ/b energy-per-bit FOM for readout signal path (gain+ADC) and the readout circuit can sense the signals as small as 1mV with more than 99% yield. The energy-per-bit FOM improved when the design is scaled down to a 65nm BSI CIS process and readout of a column with 24,000 pixels and 1040fps readout speed reached an energy-per-bit FOM of 0.4pJ/b. Moreover, the readout circuits of multi-bit QISs are explored. The power consumption and occupied area of different types of ADCs are studied and the most power efficient of them (SAR, Cyclic and Single-slop ADCs) were implemented in a megapixel imager with a 0.18μm CIS process.