Defense of Thesis Proposal - Jiaju Ma

“Photon-Counting Jot Devices for Quanta Image Sensor”

March 1, 2017
11:30 am - 1:30 pm
Location
335 Murdough Center
Sponsored by
Thayer School
Audience
Public
More information
Daryl Laware

Thesis Committee

Eric. R. Fossum, Ph.D. (Chair)

Jifeng Liu, Ph.D.

Christopher G. Levey, Ph.D.

Albert Theuwissen, Ph.D.

 

Abstract

 

The concept of the Quanta Image Sensor (QIS) was proposed in 2005 by the primary inventor of the CMOS image sensor (CIS), Dr. Eric R. Fossum, as the 3rd generation of solid-state image sensors after the charge coupled device (CCD) and CIS. The QIS differs from the conventional CIS in that it is sensitive enough to detect the smallest particle of light, one single photon. The QIS works like “digital film”, in which billions of tiny pixels, called “jots”, output binary data (either single-bit or multi-bit) corresponding to the number of collected photoelectrons at a high frame rate (e.g. 1000fps). In a QIS, the image pixels will be created by binning the digital jot data spatially and temporally. The combination of high sensitivity and fast readout gives this sensor a film-like exposure response curve, an exciting feature for the photography community. Noise-free data binning can also be achieved because the QIS bins digital numbers as opposed to analog voltages. The QIS is suitable for many applications besides photography because of its photon counting capability. For instance, life science imaging, space imaging, motion pictures, security and encryption.

To fulfill the required photon counting capability, an innovative pump-gate jot device was designed by J. Ma and fabricated in a 65nm CMOS process in 2015. A record-low read noise of 0.22e- r.m.s was demonstrated with significantly improved conversion gain. It was for the first time that the photoelectron counting was realized without using electron avalanche gain. The design concept and characterization results of this testing chip will be discussed.

To further implement the QIS concept, a 1Mega Jot QIS prototype chip was designed and fabricated with the latest 3D CMOS stacking process in 2016. It consists of twenty design variations including the pump-gate technique and multiple newer ideas. This prototype chip is still being characterized. The preliminary results have met the expected performance and some QIS features have been demonstrated.

 

Location
335 Murdough Center
Sponsored by
Thayer School
Audience
Public
More information
Daryl Laware